1. Field of the Invention
The present invention relates to the field of Electro-Static Discharge and overdrive gate protection circuits for MOSFET circuits. Specifically, the present invention relates to zener diode and thyristor gate protection circuits and is described in the context of a DMOS power device.
2. Discussion of the Related Art
Electrostatic Discharge (ESD) presents a special problem for semiconductor devices and particularly for metal oxide semiconductor (MOS) types of structures. The high voltage transient signal from a static discharge can bias an object with more than 10,000 Volts. The unique hazard in MOS devices is the high electric field that can develop across a relatively thin gate dielectric used in the normal course of operation of the device. The gate dielectric, which is often oxide, can rupture under high electric field conditions, when the charge built up on the gate penetrates the gate oxide which normally acts as an insulator. The effects of the permanent damage caused by the rupture may not be immediately apparent; therefore, the possibility of gate oxide rupture constitutes a realistic reliability concern.
Common power MOSFETs have no protection against ESD (electro-static discharge) or excessive voltage signals applied to the gate. Silicon dioxide (SiO.sub.2) is often used as the gate dielectric in MOS devices. Typically, the rupture voltage for SiO.sub.2 can be as high as 10,000,000 Volts per centimeter. Modern MOS devices may have operational gate oxide of 400 .ANG. thickness. Therefore, the realistic rupture voltage for such a device is only about 40 V. One of the primary causes of ESD is contact with the human body during product assembly or maintenance. The "human body model" for ESD conditions typically involves a resistor in series with a capacitor. The capacitor in the human body model is very large in comparison to the gate capacitance of the MOS power device, which typically have higher gate capacitances than other types of MOS devices. Thus, the human body appears to the power device as a high voltage battery during an ESD event.
Because ESD conditions are common in many working environments, many commercial MOS devices are equipped with self-contained ESD protection systems. These can be discrete or integrated with the main functional circuitry.
One method for protecting the gate of the devices from voltage above the oxide breakdown employs back-to-back diodes constructed in the polysilicon gate and then connected to the source. This method is effective in improving the ESD rating of the MOSFET gate, and for avoiding over voltage damage; however, gate-source leakage current increases significantly since diodes constructed in polysilicon have much greater leakage current than in monocrystalline silicon. Maximum gate leakage current typically increases from 100 nanoamps to 10 microamps using this method. Some manufacturers have constructed other components in conjunction with the polysilicon diodes thus adding some limited control functions such as over current protection.
An example of a typical ESD protection structure commonly implemented on a CMOS IC is shown in FIG. 1. In the circuit of FIG. 1, a large invertor is formed by the N-channel MOS 101 and the P-channel MOS 102. Zener diodes 103 and 104 protect the gates of the power transistors 101 and 102 from very high voltages; zener diodes 105 and 106 protect the gates from very low voltages. Each zener diode pair is configured to pointing in opposite directions so that for current to flow in either direction across the pair, one zener breakdown voltage (plus one forward-biased diode drop) must be incurred. The reverse breakdown voltage in a zener diode is dependent upon the characteristics of the diode, but is typically much higher (on the order of several volts to tens of volts) than the forward-biased diode (on the order of 0.6 to 0.8 Volts). For extremely high positive or negative voltages, both diode pairs may conduct until the input voltage reaches a sufficiently low positive or negative voltage so as to cause one of the pairs to turn off. The pair 105 and 106 will turn off first for high positive voltages, while the pair 103 and 104 will turn off first for high negative voltages. The diode pair that remains on will continue to conduct until the input voltage reaches an even lower positive or negative voltage so that none of the protection diodes is turned on. The zener diodes are fabricated such that they their reverse breakdown voltage plus one forward-biased diode drop is less than the rupture voltage for either power transistor 101 or 102.
Polysilicon diodes are sometimes used for ESD protection on the gates of power devices. FIG. 2 illustrates one way to fabricate a polysilicon zener diode protection circuit such as shown by elements 103 and 104 in FIG. 1. The source metal 201 connects to a series of polysilicon regions alternately doped as N and P type. The gate metal 202 connects to one of the polysilicon regions at the end of the series. The source metal is insulated from the drain 203 which is the N- epitaxial layer by a thin layer of gate oxide 204. Thick field oxide 205 insulates the back to back diode series and the gate metal from the N- drain 203.
However, the use of polysilicon to produce a diode suitable for ESD protection circuitry has the disadvantages that the diodes are leaky, and thus a substantial leakage current may result. In addition, the fabrication process for polysilicon diodes is somewhat complicated. Moreover, the current-voltage characteristic of the polysilicon diodes is a monotonic function having no "snap back" or thyristor-like behavior. In other words, even after breakdown occurs, a high voltage must be maintained across the junctions in order to maintain the current. Because a high voltage is required in order to cause the keep the diodes in a conduction state, a low current to power ratio is achieved. In other words, because prior art structures for ESD protection include polysilicon diodes which inherently have high leakage currents, increased ESD protection requires increased power dissipation in those prior art devices.
DMOS (Double Diffused MOS) transistors are a type of MOSFET (Metal On Semiconductor Field Effect Transistor) using diffusion to form the transistor channel regions. The typical application for DMOS transistors are as power transistors. In order to provide high voltage circuits for power integrated circuit applications, DMOS is presently the device of choice. DMOS transistors are widely used in applications which require high power capabilities. DMOS transistors provide the higher current per unit area when low forward voltage drops are desired.
In a typical discrete DMOS circuit, several DMOS transistors are fabricated in parallel. Therefore, on a typical discrete DMOS semiconductor, the DMOS devices share a common drain contact (the substrate), their sources are all shorted together with metal, and their gates are shorted together with polysilicon. The discrete DMOS semiconductor thus behaves as if it were one large transistor, even though it is often physically constructed using an array or matrix of smaller transistors all connected in parallel. For a discrete DMOS semiconductor, it is desirable to maximize the conductivity per unit area of DMOS transistor array when it is turned "on" by the gate.
One of the new application trends for DMOS technology is in power management and switching in battery operated circuits such as portable computers and cellular telephones. One of the significant requirements in future circuits is to reduce power consumption and thus extend the time between battery charging cycles. New circuits are using lower voltage integrated circuits that have supply voltages of 3.3 volts and less to reduce the demand on the batteries. The MOSFET components are used to shut down power to unutilized circuits and for driving transceivers. To keep pace with the decreasing power supply trends, the MOSFET components must be capable of operating at lower gate drive conditions. If the MOSFET will no longer be driven up to 10 volts, the need for high gate voltage ratings becomes unnecessary except to limit ESD susceptibility.
In one typical prior art process, both the channel and heavy body diffusions are placed under the gate bond pad as in FIG. 4. The interlayer dielectric is continuous under the pad to minimize gate-source and gate-drain capacitance. The gate metal only contacts the polysilicon gate around the gate pad periphery or in the gate busses or runners.
FIG. 4 illustrates a normal gate bond pad structure and the edge of the DMOS array having no ESD protection. The N+ regions 401 and 402 are source regions which are connected to source metal. (The connection of the source metal 403 to the N+ source region 401 is not shown.) The gate metal pad 404 is insulated by interlayer dielectric and is connected to the gate polysilicon 406 in a part of the chip not illustrated in FIG. 4. FIG. 5 illustrates a typical N-channel DMOS circuit element realized by the structure of FIG. 4, for example.
While it is possible to incorporate the diode structure into the polysilicon without additional mask steps, it is likely that, in order to achieve the best possible performance of both the MOSFET and its gate protection diodes, additional masking steps would be preferred.
Utilizing modern state-of-the-art smart power technologies it is possible to have very sophisticated gate protection schemes. Smart power products are power devices which incorporate a few small signal devices on the chip with little or no added process complexity in order to provide protection and diagnostic functions to the power device with very little additional cost. These technologies can integrate a wide variety of CMOS control elements with multiple DMOS output devices. Other smart power technologies use lateral DMOS structures to accomplish the required integration. However, most of these process technologies require double the number of masking operations, compared to discrete devices, to achieve the desired control structures. Because the cost of a chip is in part a function of the number of masking steps necessary in fabrication, the cost per unit area of silicon is significantly higher using these processes which require a greatly increased number of masks to implement the gate protection devices.
In addition, excessive voltage applied to the drain, as in inductive switching applications, in which no external drain voltage protection has been provided, can often cause excessive heating or damage when the device dissipates the inductive energy while conducting the current across the diode 501 in FIG. 5 in avalanche breakdown.
As fabrication technology allows increasing further miniaturization of the semiconductor features, the gate oxide becomes thinner; therefore, MOSFET devices will become more prone to ESD damage and voltage transients on the gate. Thus, there is an increasing need for effective gate protection mechanisms. Therefore, it is desirable to produce a gate protection mechanism having low process complexity, having very little or no leakage current, and providing a high current carrying capability (high current to power ratio) even at relatively low voltages.